Responsible for IC analog chip/IP layout

Responsible for verification of the layout with Cadence DRC/LVS

Responsible for chip floorplan

Assist the project tapeout

Requirement

Bachelor's Degree in Electrical/Microelectronics/Electronic Engineering, or equivalent

Solid understanding on IC technology and circuit design

2~3 years experience in Candence Virtuoso

Ability to work effectively and take responsibility

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