Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Candidate must have a Bachelor's degree in Electrical/Computer Engineering and 5+ years of experience in relevant areas or related experience in lieu of degree.
• Experience with logic design and microarchitecture of an IP or a block within an IP.
• Experience working with cross functional teams like architecture, integration, verification.
• Candidate must have unrestricted permanent right to work in Costa Rica
• Advanced English level

Preferred Qualifications:

• Understanding of design globals like clocking, reset, boot and power management flows, low power design techniques, and security.
• Understanding of RTL quality checks like CDC, Lint, VCLP, LEC.
• Understanding of other domains like pre-si DV, physical design.

Inside this Business Group

The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center.  Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.