Key Job Functions:

• Understand the architecture of the graphics chip and functional block being designed
• Be responsible for developing, maintaining the graphics power tests and power estimation flow
• Participate IP/SoC level graphics power estimation and post-silicon bring-up
• Debug power bugs of graphics chips

Requirement and Preferred Experience:

• BS, MS or PhD in Electrical Engineering or Computer Science.
• 8+ years of ASIC verification or low power design/verification experience
• Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Advanced programming knowledge on Verilog/SystemVerilog, Perl
• Requires demonstrated technical expertise in the areas of low power design/verification methodology and power estimation
• Knowledge on PTPX is a plus
• Demonstrates leadership ability preferred.
• Strong problem-solving skills
• Good written and fluent oral English
• Good communication skill and teamwork spirit

上班地址：环科路669号凯瑞大厦