You will be responsible for identifying, investigating, and implementing solution of product related yield and PHI (product-health-indicator) limiters. The MPE Yield engineer ensures the testability and manufacturability of Intel Data Center products from Pre-Silicon stage through production ramp with specific emphasis on yield analysis to meet both quality and cost requirement.

• Investigate and debug complex test and Si material related yield issues.

• Analyze and evaluate component performance to ensure optimal match of component requirements with production equipment capability.

• Come up with innovative solutions.

• Define the backend product yield roadmap and follow through with execution per project milestones.

Although the key focus areas of this position involve investigating product yield issues, identifying root-cause and delivering solutions, MPE Yield engineer also works closely with a wide range of partners and stakeholders across Intel, including Product Development, Process Development, Design, Architecture, Sort, Test Equipment engineers, labs and Manufacturing teams in order to deliver a high-quality technology for HVM ( High Volume Manufacturing ).

Additional responsibilities and qualifications include but are not limited to:

• Demonstrate solid willingness in data collection and analysis.

• Apply engineering application tools (JMP, SQL python, etc.) to perform data analysis and solve complex problems.

• Establish and deliver yield improvement roadmaps.

• Have in-depth knowledge of Intel Testing methodology and HVM testing environment.

• Partner with test content owners to analyze and resolve yield limiters.

• Work closely with FSM (Fab SORT Manufacturing) and TD on incoming materials quality indicators, test conditions and yield correlation to backend.

• Collaborate with business groups and cross-site partners (e.g. ATD, Fab, ATM, Design) to accomplish high quality and cost-effective Yield goals for HVM.

NOTE: Work location for this position is Santa Clara, CA

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor of Science in Electrical, Computer or related engineering discipline and 6+ years of experience

OR

Master of Science in Electrical, Computer or related engineering discipline and 3+ years of experience with:

• Yield analysis.

• Data analysis (JMP, SQL, Python, etc.).

• Semiconductor Manufacturing process knowledge.

Preferred Qualifications:

• Intel Process Technology.

• Manufacturing testing (ATE, debugging).

• Knowledge of semiconductor device physics.

• Model based problem solving.

• Innovative thinking and leading cross teams debug working groups are critical as well.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.