• Support IP layout porting efforts.
• Work with BU to implement IPs with foundry technologies.
• Work with BU and IP mask designers to complete IP layout design for test chip validation and product use.
• Support full chip DRC/LVS and TO gatekeeper

Qualifications

• 7 years of experience with proven record of delivering high quality layout
• Expertise in Virtuoso EDA tools and familiarity with UNIX environment
• 5 years design experience in analog or stdcell layout design is a plus
• Collaboration and team lead skills

Inside this Business Group

Intel's Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.