Develops and supports high speed custom memory HIPs for next Intel client products. The team acts as "SRAM Center of execution" and includes CKT designers with different level of experience.
SRAM COE team is responsible to develop and support SRAM shared library, design and verification methodology , working closely with "Advanced Design" , post and pre silicon teams. In addition, team responsible for execution and development of SRAM IP blocks to SOC partitions. SRAM memories are the biggest memory blocks used on CPU chip. Each memory block requires close work with architecture team in order to reach best area utilization , lowest power and required frequency.

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Qualifications

B.Sc. in electrical engineering from a known university
Knowledge in circuit design is an advantage.
Knowledge in various memory design like ROM, RF and SRAM is an advantage.
Location: Haifa.

Experience in FE/BE high speed digital design

Leadership or managerial experience - advantage

#C2DG_IL

The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.