Creates bottoms-up elements of chip design, cell, and block level custom layouts, top level floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, full-chip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.

Qualifications

Minimum Qualifications:

• B.S in Electrical Engineering or equivalent technical degree
• Substantial work experience as a Physical Design Engineer
• Memory domain knowledge
• Good written and Verbal Communication

Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

Employees in Intel's NAND Product Group deliver solutions that are transforming computing across all segments from data centers to Ultrabooks. They invent, develop, bring to market and support customers with leading-edge NAND flash memory and system level solutions such as solid state drives (SSDs). SSDs are accelerating performance for gaming enthusiasts, reducing total cost of ownership for IT managers of data centers and improving security and reliability for businesses. This dynamic group is strategically positioned to become the leading Non-Volatile Memory solution supplier for the compute segment and is a key to expanding markets and continuing the growth for Intel.

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.