This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the DE Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools. As an ASIC Auto Place and Route APR Technology Development Engineer you will be responsible for, but not limited to the following: - Responsible for development of ASIC Auto Place and Route design flows and collateral using Synopsys Fusion Compiler and/or Cadence Innovus and/or Siemens Aprisa tools. - Perform detailed evaluation of tool run results to validate proper tool behavior and identify root cause for any discrepancies found. - Develop and enhance automation scripts for tool regression and quality. - Responsible for generation and quality checking of APR techfiles and other required tool collaterals. - Develop and enhance automation scripts for collateral generation and quality. - Develop and test Engineering Design Automation EDA tools and create flow scripts to analyze and test design methodologies. - Responsible for designing deploying and testing efficiency of tools in achieving design goals and collaborating with design teams on methodology development. - Candidate should be able to apply design methodologies to help execute projects effectively and successfully with high quality.

Qualifications

The candidate must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications You should have Bachelor/Master in Electrical Engineering or Computer Engineering 6+ years of industry experience with Specific knowledge in: - ASIC standard cell design using Auto Place and Route (APR) - ASIC Design Flows - Tcl - Perl, Python or Ruby nice to have Preferred Qualifications - Extensive knowledge of Cadence Innovus, Synopsys Fusion Compiler or Siemens Aprisa tools - Familiarity with semiconductor design rules and physical verification #designenablement

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.