Microelectronic Packaging Engineers in Substrate Packaging Technology Development (SPTD) provide project management, advanced package design, pathfinding and development for integrated circuit or semiconductor assemblies, various other electronic components and/or completed units.

Backend Litho Area is looking for an experienced Packaging R and D Engineer to join the team to lead developing and ramping advanced backend bump scaling technologies.

The candidate will be responsible for, but are not limited to:

- New materials and technology development in backend lithography processes, including lamination, coating, exposure, develop, strip, cure, plasma etch and other wet processes.
- Thermal/mechanical/electrical design, analysis, and development of electronic packages. Defines overall package performance and specification.
- Process development and transfer supporting pathfinding and development of different technologies.
- Innovated model based problem solving through application of fundamental technical knowledge, experimental design and statistical methods.
- Build competency on new equipment/processes and develop emerging TD/PF technologies to effectively support growing roadmap.

Candidate should exhibit the following behavioral traits/skills:

- Self-motivated with written and verbal communication skills.
- Model based problem solving and analytical skills.
- Flexibility in changing priorities and responsibilities to support business needs.
- Capable to work independently and collaboratively.
- Demonstrate technical innovation and leadership. Deliver results for complex time critical technical projects.
- Apply fundamental science and engineering concepts in development to create novel solutions.
- Combine solid engineering judgement and data analysis to draw fundamental conclusions, build models and design experiments.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.


Minimum qualifications:

- Candidate must possess a MS with 4+ years of experience or Ph.D. degree with 2+ yrs experience in Electrical Engineering, Materials Science, Physics, Chemical Engineering, Mechanical Engineering, or other applied engineering field.

Preferred qualifications:

5+ years of experience in at least 2 of the following:

- Vacuum system, plasma technology, photolithography, lamination, coating, wet process, material development, or other advanced semiconductor microfabrication and packaging R and D
- Thermal mechanical properties of materials, fluidics, material science and characterization techniques such as optical microscopy, SEM, TEM, FTIR, XPS, AFM, XRD, etc.
- Design of Experiments (DoE), SPC, PCS, and RFC.
- Data analysis skills using JMP and SQL scripting.
- Tool development, tool installation and qualification.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.