At Intel, every day, we create world-changing technology that enriches the lives of every person on earth. So if you have a big idea, let’s do something wonderful together. Join us, because, at Intel, we are building a better tomorrow. Intel’s mission is to shape the future of technology to help create a better future for the entire world. By pushing forward in fields like AI, analytics, and cloud-to-edge technology, Intel’s work is at the heart of countless innovations. From major breakthroughs like self-driving cars and rebuilding the coral reefs to things that make everyday life better like blockbuster effects and improved shopping experiences they’re all powered by Intel technology. With a career at Intel, you have the opportunity to help make the future more wonderful for everyone.

In this role, you will be part of Intel's Barefoot Division (BXD is known to design world’s first end-user programmable Ethernet switch meeting the needs of hyperscale data centers) physical design team working on innovative programmable switch ASIC roadmap. You will engage with Architecture, DFT, and packaging to arrive at optimal chip planning early in the design cycle. You will be part of our physical design team working closely with cluster and partition leads to comprehend design challenges and arrive at optimal floorplans. You will play a critical role in die size estimation and evaluating RV tools, IR drop and EM methods, ESD and flows. Your work will involve meticulous planning of various aspects of floor planning for optimal data flow for high pin densities and to facilitate high confidence timing closure and routability. With your broad understanding of physical design, you will play a critical role in identifying and solving a multitude of design issues at partition/cluster and full chip.

Qualifications

Education Requirements

BS in Electrical or Computer Engineering or related field plus 5 years of semiconductor industry experience.

Minimum Requirements

3+ years in physical design and experience on block closure

3+ years of experience in floor planning and global timing verification, and Physical Design Verification Flows

1+ years of experience IR drop/EM analysis and developing guard bands for desired yield and performance.

2+ years of experience in floor planning tools such as Synopsys ICC2 or Cadence Innovus

1+ years of experience working on advanced process nodes such as 7nm and below.

2+ years of experience with SoC issues such as multiple voltages and clock domains, ESD strategies , low power design

Preferred Qualifications

4+ years of experience in advanced package technologies

3+ years of experience Hierarchical design approach, top-down design, budgeting, timing, and physical convergence

3+ years of experience Integrating IP from both internal and external vendors and to specify and drive IP requirements in the physical domain

3+ years of experience with large SoC designs with power/performance upwards of 1GHz and die size challenges.

1+ years of experience in various process-related design issues, including Design for Yield and Manufacturability, multi-Vt strategies, and thermal management

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.