The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changes the world for the better brings. We work every single day to design and manufacture silicon products that empower individual's digital lives. If you love to solve technical challenges that no one has solved yet or enjoy working with multiple teams to deliver Intellectual Property solutions for products that impact customers lives, then, come explore these opportunities with us

As a Physical Design Engineer, you would be responsible for creating custom layout for bottom-up elements of chip design including, but not limited to:

• Transistor, Cell, and Block-level custom layouts, floor plans, abstract view and schematic-to-layout generation.

• Layout verification and debug to enable physical design development, including observing and intercepting parasitic extraction results.

• Producing wire load models, Quality clock generation, custom polygon editing, floor-planning, full-chip assembly, packaging and verification.

• Troubleshooting a wide variety of issues including difficult design concerns and apply proactive intervention.

• Scheduling, staffing, executing, and verifying complex chips development and execution of project methodologies and/or flow developments.

• Requires knowledge and practical application of analog/custom physical design tools and methodologies.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

The experience listed below would be obtained through relevant previous job and/or internship experiences.

Minimum Qualifications:
Candidate must have a Bachelor's degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS) with applicable projects or industry experience.

OR

Master's degree in Electrical Engineering (EE), Computer Engineering (CE) Computer Science (CS) with experience in:

• Electronic circuit functionality and behaviors.

• Complementary Metal Oxide Semiconductor CMOS and Very Large Scale Integration VLSI component design principles.

• Familiar with Electro-migration, self-heating, and other reliability concepts.

• Working knowledge of Custom Physical Design requirements for digital, mixed-signal and analog circuitry.

• Working knowledge of various verification flows for DRC and LVS tools.

Preferred Qualifications:

• Must understand how to run extraction tools and how to use that feedback to guide physical design.

• Experience with electro-migration, self-heating issues and how to mitigate them.

• Experience in Analog Physical Design requirements for digital, mixed-signal and analog circuitry.

• Experience in Cadence design flow, Virtuoso, and/or comparable tools.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.