• Creates bottoms up elements of chip design including but not limited to FET, cell, and block-level custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, auto place and route algorithms, floor planning, full-chip assembly, packaging, and verification.
• Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
• Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.
• Requires expansive knowledge and practical application of methodologies and physical design.

Qualifications

• The ideal candidate would have a minimum of 5 years experience in laying out analog circuits on advanced FinFet technologies.
• He/She would be experienced in running extractions for circuit simulations as well as be very familiar with reliability requirements on a given technology.
• The candidate is expected to be familiar with the industry-standard tools as well as have the ability to independently debug tool issues.

The candidate should have at a minimum a bachelors degree in an engineering/science field.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.