In this role responsibilities may include:

Creates bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, AIP and CBB level floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, wire load, clock generation, customer polygon editing, auto place and route algorithms, floor planning, Family level assembly and verification.

Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs (both local and remote) executes and verifies complex chips development and execution of project methodologies and/or flow developments.

Requires expansive knowledge and practical application of methodologies and physical design.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelors in Electrical/Computer Engineering Science or related field and 1+ year of experience -OR- a Masters in Electrical/Computer Engineering Science or related field and experience in:

• High speed analog physical design experience

• 1- 5 year of analog physical design experience

• Current industry layout tools (preferably Cadence Virtuoso)

• Current industry validation tools (Cadence, Synopsys)

• Working with remote resources from differing GEO locations

Preferred Qualifications:

• Scripting experience in Skill (Cadence)

• Cadence Virtuoso expertise including PCell generation

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.