We are looking for a Physical Design Methodology Engineer to help us develop Test Chip Lead Vehicles, which are primarily used by our Design Enablement (DE) team for Intel's next generation process development and high-volume certifications. This role primarily focuses on the layout domain and encompasses engagement with manufacturing on cutting-edge process nodes. Responsibilities include facilitation of hierarchical layout convergence, correct-by-construction assembly, IP integration oversight, and owning and driving the qualification of the overall design to meet tape-out requirements.

This role includes, but is not limited to, the following activities:

• Developing layout design methodology and productivity automation for cutting edge process nodes at 10nm and below.
• Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements.
• Orchestrating mock full-chip assembly and tape-ins in preparation for the real thing and provide package and tape-out partners with representative data for planning and product prep.
• Building and supporting tools, capabilities, methods, and work models for global layout design and convergence.
• Working with tool/flow owners and vendors for ongoing tool/methodology improvement.

The ideal candidate should exhibit the following behavioral traits:

• Verbal and written communication skills.
• Ability to work well both autonomously and in an intensive, cooperative team environment.
• Exhibiting strong interest in Layout design Motivation to continuously learn and drive to push improved layout productivity and efficiency.

The is a entry / early-mid level position. Compensation will be given according to experience.

Qualifications

Minimum Qualifications:

• Master's degree in Electrical Engineering or Computer Engineering
• 6+ months of intern or professional experience in the following areas: Cadence Virtuoso XL; Design rules check (DRC) and Layout vs Schematic (LVS); Layout, floor-planning experience; Scripting using one of the following: Perl, Python, TCL

Preferred Qualifications:

• Knowledge of device physics, electrical behavior of materials and insight into ways to improve reliability and manufacturability of CMOS device in advanced process technologies.
• Floor planning with ICC2-DP and ability to customize the flow based on design needs.
• Exposure to Runset development using ICV/Calibre to facilitate automation to improve layout productivity.
• Project Management skills in coordinating and tracking the entire design cycle of a project from layout planning to GDSII/oasis.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.