Taiwan - Hsinchu

Candidate will be DFT expert in PTE (Product & Test Engineering) team to drive yield, test, and quality improvement at wafer foundries by collaborating with yield, product, and test engineers. Responsibilities will include to analyzing, interpreting, and driving solutions to semiconductor test failures and test escapes from ATPG, Memory BIST, retention, and functional test using WS, FT, SLT, and e-test data; ATPG and memory diagnostics; BIST controller analysis; static timing analysis; and physical design information. Depending on candidates skills, knowledge, and experience, opportunities for advanced development in simulation and diagnostics are available.

Knowledge of semiconductor design for test (DFT) concepts and practices; ATPG architecture, pattern generation, fault behavior, fault models, diagnostics, data paths, and test output structure; memory BIST architecture, pattern generation, algorithms, repair methodologies, and testing including data collection; and ATE systems and test hardware (probe cards, load boards, etc.).

Experienced candidates or new college graduates who have research specializing in ATPG or MBIST will be considered.

Test patterns and test methodology for Laser Voltage Imaging, Dynamic Laser Stimulation, and Photoemission Microscopy; failure analysis methodologies, applications, and limitations; transistor operation; semiconductor FinFET fabrication and structure (FEOL, MOL, BEOL); advanced statistical analysis (DOE, linear and logistics regression; handling of non-normal distributions), semiconductor yield analysis; business-level English (speaking, writing, reading)

Master's or Doctorate in Electrical Engineering, Physics, Materials Science, or related discipline required.