Responsibility:

• Responsible for defining low power methodology & Driving Low power design cross multi-IP/SOC teams
• Responsible for power-performance modeling, Pre-Silicon power estimation, & Post-Silicon power characterization
• Responsible for defining Vdroop and IR-drop optimizing design methodology
• Responsible for defining Post-silicon power binning strategy
  

Requirements:

• MSEE with 5+ years or Bachelor with 10+ years of experience on low power design & optimization;
• Strong background of Low-Power technologies
• Solid working experience on Pre-Si ASIC design, Post-Si characterizing & Yield analyzing
• Solid programming in Verilog HDL; skillful in C/C++, Perl, Python are big plus
• Good in verbal and written English

上班地址：盛夏路61弄张润大厦2号楼3层302室