DSP algorithms simulation using advanced simulation tools, while performing basic tradeoffs: power die size performance. HW implementation coding, validation and synthesis. Lab Validation (SV) basic abilities.

Qualifications

M.Sc or higher in Electrical engineering, with study fields: VLSI, Mixed-signal/Analog, Signal processing. Familiarity with PHY architectures for HSIO/SERDES systems, with emphasis on Ethernet standards, PCIe, USB, TB, etc' 5+ years of experience and knowledge in at least two or more of the following fields: DSP, system identification, modeling, top-down design, signal integrity, mixed-signal subsystems, high speed ADC 5Gsps, Firmware/real time. 3+ years of experience with at least three of the following tools/languages: Matlab, Simulink, Python, Verilog, C++, JMP Experience in lab work for design validation basic equipment operation, scripting for test automation, data analysis and post processing, etc. Basic understanding of analog / mixed-signal circuits high level is a must. Experience in writing technical presentations, design documentation and technical material is a plus

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

Israel, Jerusalem