RESPONSIBILITIES:

• Develop micro-architecture for GPU blocks based on architecture requirement.
• Develop RTL codes for GPU blocks in Verilog HDL
• Hardware optimization for GPU blocks on performance, power and area
• Synthesis and closely working with physical design for timing closure

REQUIREMENTS:

• MS degree of EE with 8+ years working experience in ASIC Company
• Strong RTL design capability and has experience on large digital ASIC product
• Familiar with front-end ASIC design flow and EDA tools
• Familiar with UNIX/Linux working environment and script language (tcl, perl etc.), C/C++ programming preferred
• Fluent English on communication, presentation and writing documents
• Work independently with limited supervision, strong sense of work planning and on-time delivery
• Computer architecture and computer arithmetic knowledge is a plus
• Computer graphics knowledge is a plus

上班地址：张东路1387号46-49栋