Delivers innovative and state-of-the-art DFX architecture and microarchitecture solutions for Intel PCH and SOCs. The team has complete engagement throughout Intel silicon life cycle (product concept to post silicon) and assumes end to end ownership of design, integration, validation and test content enabling for manufacturing. As a Chipsets System on a Chip (SoC) DFx Design Engineer, a typical day may include, but is not limited to:

DFx Architecture Engineer
� Drive early technical readiness (TR) review with internal stakeholders to refine requirement and define strategy for implementation, execution and validation of the design.
� Deliver the feature HAS/micro-architecture HAS for design/validation team to execute.
� Partner closely with the RTL Design and Validation team to ensure quality of design implementation and validation.
� Review progress and key challenges on a regular basis with senior leaders from the organization. A key avenue to showcase innovation and continuous improvement to leaders.
� Work closely with IP office and External Foundry for new IP definition to ensure test and debug requirements are comprehended for new IPs. Ensure requirements are documented in Statement of Work between Intel and Vendor.
� Participate and engage actively in multiple product power on for support for early boot debug for system and sort. Review through the content enablement progress throughout the Manufacturing Life Cycle to ensure health of silicon and DPM goals being met.
� Close partnership throughout product execution with multiple stakeholders (QRE, Manufacturing, Post Si, Burn In, Design Leadership, Structural Design) to ensure execution stays in course meeting all the agreed requirements.
� Knowledge and hands-on experience on peripheral protocols such as I/O design protocols (SATA, PCIe, USB and others) is an added advantage

Qualifications

Bachelor/Master of Engineering or Science degree in Electronic, Electrical or Computer Engineering
Additional qualifications include:
Familiar with UNIX, and well-versed in Verilog or C Programming
Knowledge in RTL integration and validation methodologies
Knowledge in Design-for-X (DFx), where X is Test (DFT), Debug (DFD), Manufacturing (DFM) or Validation (DFV)
Familiar with Scan design, methodology, coverage analysis and test validation
Ability to communicate well with counterparts and key stakeholders including cross-site partners

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.