General Job Scope
- Below describe general DFx job available, actual assignment will depend on Interview assessment and candidate interest.

DFx micro-Architecture Engineer
- Drive product early technical readiness (TR), which require to understand customer requirement and plan for design definition solution.
- Besides DFx architecture, advantage will go to those familiarize in other peripheral protocols such as I/O design protocols (SATA, PCIe, USB and others).
- Close handshake with RTL design team to ensure implementation is meeting definition expectation. In such, DFx uArch will work with RTL design, Pre-Si Validation team within DFx.

DFx RTL Integration and Design Engineer
- Require RTL coding, pick up different RTL tool-based solution. Integrate all other DFx sub-IPs into one stop DFx complete RTL solution (a.k.a DFx IP). Next insert this One Stop DFx complete logic (a.k.a DFx IP) into Main PCH chip. Along the process will require signal/clock connection, timing convergence and etc.
- Responsible to patch RTL logic for flawless area along execution phase. Ensure zero RTL design errors (bug free) as ultimate goal for DFx features.
- Insert MemoryBIST logics to PCH, as part of the DFT features to enable High Volume Manufacturing (HVM) Memory screening through tests (Post Silicon team).
- Require good communication skill due to collaborate with geo-diverse teams (full chip, structural design team, other IPs team) in analyzing, debugging and identifying the root cause of issues that arise.

DFx pre-silicon validation Engineer
- Understand DFD, DFT or DFV features through spec reading, release test plan and develop relevant test script. Ensure all the RTL Design being validated well to eliminate design flawless to customer.
- Execute Tests script (DFx Tests) with time guide, debug issues and implement fix. Report out test result timely and perform necessary test enhancement steps.
- Drive test review with counterparts such as Pre-silicon full chip team, IP team, post silicon tester team, board team and etc. Thus require collaborate closely with other function group for test debug, analysis and root cause.
- In additional, collaborate closely with Post silicon PDE team to enable HVM (high volume manufacturing) testing capability
- Familiar DFx test Island (Test environment) for validation efficiency, enhancement purpose.

Qualifications

Bachelor/Master of Engineering or Science degree in Electronic, Electrical or Computer Engineering.
At least 4 years of working experience.
Additional qualifications include:
Familiar with UNIX, and well-versed in Verilog or C Programming.
Knowledge in RTL integration and validation methodologies.
Knowledge in Design-for-X (DFx), where X is Test (DFT), Debug (DFD), Manufacturing (DFM) or Validation (DFV).
Familiar with Scan design, methodology, coverage analysis and test validation.
Ability to communicate well with counterparts and key stakeholders including cross-site partners.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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