As a structural design partition owner, you will be part of the design team working on the next generation Xeon server product SOCs. This will be a fast-paced dynamic environment where you will work on a high performance design team focused on a wide spectrum of structural design and backend physical design activities.

Your role will include aspects of partition design from RTL to TI-ready GDS. You will work closely with silicon architects, RTL design engineers, internal/external IP vendors, the DFT and DFD teams, and get exposure to all aspects of product development.

You will be part of a Xeon SoC product design team that encourages innovation, learning, team collaboration and thinking outside of the box to address all of our product development challenges.

Responsibilities include synthesis, place, clock and route, timing closure, functional equivalence, power, reliability, and layout and DRC convergence. You will be involved in executing all aspects of physical design to enable our team to meet project goals. Good knowledge of process, Fusion Compiler, ICC2, and Prime Time are required.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Computer or Electrical Engineering with 5+ years of industry experience -OR- a Masters degree in Computer or Electrical Engineering with 3+ years of industry experience and expertise in synthesis, place and route static timing analysis using Primetime tools, Design for Test flows, and low power design.

Preferred Qualifications:

• Deeper understanding of a few aspects of physical design analysis and convergence.
• Proven track record of strong partnership and collaboration with managers, RTL design, and other partner teams.

• Experience and knowledge in Functional Equivalence and/or UPF/VCLP.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, California, Santa Clara;US, Colorado, Boulder;US, Colorado, Denver;US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro;US, Oregon, Portland

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$97,500.00-$146,340.00

Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.