To work on Intel next generation CPU SoC using advance process technology. Need to be familiar with industrial EDA tools from Synopsys and or Cadence Design System. The candidate is required to implement structural physical designs

Your responsibility:

• Understanding & hands on experience in full IC and block level SoC Physical Designs.
• Proactively demonstrating the knowledge in synthesis, FEV, STA.
• Proven the Experience Design floorplan, Clock Tree Synthesis, Power Network Synthesis, Place and Route, Physical Verification (DRC, LVS), DFM, SI(Xtalk).
• Verifying Low-Power design, UPF.
• Performing IR Drop/EM check.

Qualifications

Your background: 

• Fresh graduate. 
• Bachelor or Master’s Degree in Electronics Engineering/Telecommunications, Computer science, Physics electronics.  

Required technical skills: 

• Synopsys: Fusion/ICC2, StarRC, Primetime, VCLP. 
• Cadence: Innovus, Quantus, Tempus. 
• Mentor: Calibre. 
• Proven experience in IC tape-outs. 
• Deep understanding of the RTL2GDS flow design cycle. 
• Understanding of CMOS process. 
• Excellent scripting skills and CAD automation techniques. 
• Linux/Unix proficient. 

Additional requirement:  

• Good English skills.
• Strong analytical, problem solving and decision-making skills with the ability to independently draw conclusions. 

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.