To work on Intel's next generation Client CPU SoC with latest process technology in the era of hyper scale computing.

Responsible to implement complex structural physical designs including synthesis, floor planning, power-grid and clock tree designs, place and route (PnR), Static Timing Analysis (STA) timing budgeting and closure, RC-extraction, DFM and DRC clean-up.

Verify the physical designs through all the verification and sign-off flows, such as functional equivalency verification (FEV), timing/performance verification(PV), Signal Integrity/Noise, layout design rules verification (LV), reliability verification (RV) and power optimization and convergence.

The candidate has the opportunity to involve in defining Structural Design methodology and developing/pioneering design flows with other cross functions stakeholders.

The candidate is expected to be very familiar with Industrial EDA tools and be able to provide technical consultation and design trade-off.

Qualifications

Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of experience.

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.