Join the XSD department under XEG Division to design a new architecture of cloud computing server chip. The exciting and challenging role would in the CPUTILE PHYSICAL TIMING ENGINEER, owning all aspects of timing. On this project, the CPUTILE is a ground design in both RTL and physical design.

Qualifications

In this role, responsibilities include (but not limited to):

• Own CPUTILE timing methodology and closure.

• Collaborate with Logic Designers, FC Timing Owners, Partition Design Engineers on timing issues.

• Conduct timing rollups, budget timing constraints, and analyze/drive timing convergence with advanced and creative techniques.

• Conduct design optimizations at the higher CPUTILE level for sub-modules cross interface timing convergence.

• Provide technical leadership to the team through technical prowess and innovate problem solving.

• Capable of independently driving technical taskforces when critical issues arisen.

Minimum Qualifications:

• BS with 10+ years of experiences, or MS with 8+ years of experiences.

• Experiences in Computer Architecture and VLS Design.

Preferred Qualifications:

• Gone through full physical design cycle, from arch/feature eval related to physical design, through design execution, and to design verification and closure.

• Familiar physical integration tools, flows, methodologies.

• Familiar with Synopsys/Cadence EDA tool sets, such as Fusion Compiler, ICC, Primetime, Starrc.

• Solid scripting and automation skills.

• Adept and comfortable with diverging from default project methodologies and flows when necessary.

The ideal candidate should exhibit the following behavioral traits:

·        Solid leadership and mentorship skills.

·        Take initiative to tackle challenging problems.

·        Problem-solving skills.

·        Willingness to multitask.

·        Solid written and verbal communication skills.

·        Willing to work in a dynamic and team-oriented environment.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$113,500.00-$170,120.00

Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.