Performs logic design, Register Transfer Level (RTL) coding, IPs integration, and simulation. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Work with IP providers to integrate and validate them in testchip environment.

Qualifications

Multiple years of experience in IPs integration and fabric design (prefer Intel IOSF), including fabric configuration and generation.Good understanding of design in the latest technology process node, prefer design knowledge of 7nm and newer.Cross discipline knowledge in any of these areas such as high speed design, mixed signal design, Analog integration, RTL System Verilog, Static timing analysis concepts, APR Floorplanning, metal routing, Powergrid, Memory IO training, MRC and HAS/MAS specification documentation.Strong written and oral communication skills.Positive attitude and team player.BSEE with 10 years relevant experience or Masters with 8 year relevant experience required. Education focus should include digital design.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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