Be part of the next technological revolution. Since 1968 Intel has been imagining a better future and continually advancing and enabling the technology to build it. We are not just a chip maker, we are a technology enabler who has been responsible for incubating and developing life changing technology that ranges from cloud computing to autonomous vehicles and drone technology. We put the silicone in Silicon Valley, but that was just the beginning. Be a part of what comes next and do something wonderful today!
As a member of Intel's Programmable Solutions Group (PSG), you will use your knowledge of high-speed IO/SERDES technology, AIB and DDR to lead efforts for building state of the art SOC and enabling customers, both internal and external, to use the Structured ASIC technology. If you are a self-driven with deep knowledge in design, verification, and communication interfaces, coupled with good communication skills, this will be a great fit for you. This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space.
In this role the following responsibilities will be provided but not limited to:,
Support new product and high volume manufacture activities for wafer sort and final test ) to meet all quality, reliability, yield and cost requirements.
Create ATE test plan and develop ATE Hardware, Software solutions for WS and FT testing
repeatability and reproducibility golden units generation before production release
Test equipment (oscilloscope, logic analyzer)
Follow procedures to complete document and to provide data for meeting criteria of each product life cycle
Support RMA, test time reduction, test yield improvement activities to assure the stability and reliability shmoo
Work with cross functional teams to convert, debug patterns and to implement DC, mixed signal parametric measurements
Perform gage and interface with variety of global teams and customers
Validate tests with repeatability data
Qualifications
Minimum Education:
BSEE/MSEE or BA degree in engineering or related field
Minimum Qualifications:
7+ years’ experience as an engineer
Experience in ATE specification, configuration and programming on Advantest SmartScale, PinScale, 93K platform
Experience in development and debug, DFT, and test methodology
Experience to perform digital SERDES, DDR test methodologies and sampling theorem
Experience in programming with Scripting languages (i.e., Perl/Python) and high level languages (i.e., C/C++ or Visual Basic.)
Preferred Qualifications:
Experience in yield analysis, quality management tools, Gage repeatability and reproducibility , Cp, Cpk- (process capability)
Experience in direct dock WS testing, 2.5D testing and multiport test solution
Experience in cadence Allegro tool in ATE PCB design
Experience in pattern conversion tool
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Get email alerts for the latest"Senior Test Engineer jobs in San jose"
