In this role you will be part of Intel Special Circuit Integration Team developing solutions for chip integration and assembly using state of the art tools and technologies (5nm and beyond) for the next generation Intel products.
Team is responsible for integration of various components such as chip assemblies on package or on passive/active silicon substrates, IO circuitry and PDN networks. Daily work includes sketching conceptual design floorplans,
building coarse or refined assembly collaterals, drawing top metal connectivity solution as reference and proof of design feasibility, communication and networking with multiple teams and people.
What you will be doing in this role:
� You will be responsible for suggesting conceptual floorplan and assembly definition for the most advanced technologies and products.
� You will be responsible to build the assembly collateral and interface files.
� You will be responsible for designing reference layout for top metal connectivity of critical circuitry such as die-to-die interfaces and demanding power delivery schemes.

Qualifications

� B.Sc degree in Electrical or Computer Engineering.
� Familiarity and capability with base programming and scripting languages (as example VBA, perl, tcl or equivalent) is required.
� 1-3 years of VLSI layout experience is an advantage, especially in the field of top metal and floorplan design.
� Strong sense of innovation and self-learning skills.
� Excellent communication (written and verbal), interpersonal skills and team player

Inside this Business Group

The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.