The Advanced Design (AD) team within Design Enablement (DE) organization is looking for talented individuals to work in Memory Design or ASIC Auto Place and Route (APR) block Design Technology Co-Optimization (DTCO) domain. At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the AD team, you will join a highly motivated team of talented engineers performing all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create an optimal design OR focusing on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design.

As design engineer, your responsibilities include although not limited to:

• Support RTL synthesis and place and route experiments using internal and external vendor tools to improve Intel's product Power, Performance, and Area.

• Deal with changes in floorplan, corresponding scaling, and its impact to power, congestion, and timing for the present technology node and predict how it would impact the scaling of power, routing and timing for the next technology node.

• Help improve cell utilization and transistor density metrics by leveraging leading edge tools and methodologies.

• Able to analyze power (dynamic and leakage), performance (setup and hold), improve critical path timing, find ways to reduce congestion by making best use of available metal layers, debug tools and more.

• Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO); product/design enablement

• Memory bitcell and complex periphery IC layout and automation

• Memory array/IP design, memory circuit innovation, testchip design/execution/validation

• Pre/post-Si validation/debug to enable yield and parametric tracking/ramp

Qualifications

• Bachelor degree in Electrical Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field.

• 6+ months of work or educational experience in at least one of the following areas:

• ASIC standard cell design using Auto Place and Route (APR)

• ASIC design flow and validation

• CAD tools/flows for digital and/or analog design

• CMOS custom circuit design, simulation, layout design and verification

• Tcl programming, Unix

• Perl, Python or Ruby nice to have

• Working knowledge of Cadence Innovus, Synopsys Fusion Compiler or Siemens Aprisa tools

• Familiarity with semiconductor design rules and physical verification nice to have

• Design, characterization and verification of custom memory (SRAM, Register File, ROM) circuits

• Design trade-off of power, performance and area

• Design technology co-optimization

#designenablement

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.