Become a key member of a team participating in the physical design construction and integration of a future Intel CPU. This position requires an engineer with broad physical design and verification skills, coupled with leadership skills necessary to collaborate effectively with multiple functional teams within the CPU design team. We are looking for a talented individual to drive the physical design and convergence of a Full-Chip (FC) assembly of partitions. As a FC physical design engineer, you will perform floorplanning, pin and feedthrough planning, top metal planning, assembly of partitions, push-down partition collateral generation and management. You will also be responsible for coordinating collateral handoffs between the FC Physical Design team and other functions within back-end design such as FC timing, Clocking, Power Delivery and Partition synthesis/APR. You will drive physical design closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).

The ideal candidate should have an aptitude to work effectively with EDA tools and exhibit behavioral traits that indicate:

• Willingness to work well in a team and be productive under aggressive schedules

• Excellent written and verbal communications skills

• Self-motivated and well organized

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications
Must have either Bachelors Degree in Electrical or Computer Engineering or a related field and 6 years experience; OR a Masters Degree in Electrical or Computer Engineering or a related field and 4 years experience; OR a PhD in Electrical or Computer Engineering or a related field and 2 years experience in the following:

• CPU physical design

• Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing

• Tcl scripting

• Floorplanning and physical design closure.

• Formal equivalence, DRC/LVS, IR and electro-migration checks

Preferred qualifications:

• 15+ years of experience with the above skill sets

• Experience with Fusion Compiler, DCT, DCE, ICC2, RedHawk, ICV, Conformal, Calibre

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.