AXG Silicon Engineering SOC Team is looking for Full Chip Layout/Design Planning Lead
Responsibilities includes but not limited to

• Drive Full Chip level floor planning, Partitioning, Top Level Chip assembly across multiple SoCs
• Responsible for area estimations for congestion free designs with multiple IP
• Should have good understanding of DRC/LVS issues at full chip and subsystem level
• Responsible for IO, Bump planning, placement of external interface IP/Macros in collaboration with package team
• Planning and executing custom routing techniques such as differential, shielding, high speed bus, RDL
• Works closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence

Qualifications

Qualifications

• You must possess a Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering or equivalent with 6-8 years of industry experience in the below mentioned skills
• Hands-on experience with industry standard tools like ICC, ICCII, Primetime, Redhawk, ICV, Calibre, Conformal
• Expertise in Physical Design execution of SoC with full ownership
• Good understanding and exposure of overall SoC Cycle
• Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies
• Aware of techniques to mitigate ESD, Latchup
• Expertise and Deep knowledge in the RTL to GDSII phase of the ASIC design flow
• Exposure and experience in building 3D IC is big plus

Inside this Business Group

The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center.  Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.

Other Locations

India, Hyderabad

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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