Come join Intel's Devices Development Group organization in Pre-Silicon Validation. DDG develops SoCs for the client segment. Our strong engineering discipline drives predictable and efficient execution, and our team is passionate about building innovative products that win in the market. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs and IPs.

You will be responsible for, but not limited to:
Validation of an IP or feature, either at the IP, subsystem, or at the system level.
Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
Learning the architecture and microarchitecture by debugging failures to the root cause.
Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution.
Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible.
Developing or debugging tools and software.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Additional specializations that may be available include emulation model builds or testing system level flows and software.

Minimum Qualifications:

• Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 9+ years' experience; OR a Master's degree in Electrical or Computer Engineering or a related field and 6+ years' experience ; OR a PhD in Electrical or Computer Engineering or a related field and 4+ years' experience in the following:

• Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
• Experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM.
• Experience with writing validation plans and software to implement those validation plans.
• Experience with UNIX or Linux.

Preferred Qualifications:

• Experience with computer architecture.
• Experience with IA-32 assembly and/or Verilog programming experience.
• xperience with validation or testing experience, especially in a silicon design team.
• Experience in the fields of emulation model builds, memory controllers, or Design For Test.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.