? Understand RTL design specification and verification plan

? Develop verification testbench components and stimulus

? Analyze and conclude root cause for issues and failures

? Develop automation scripts to implement new methodologies

? Bachelor or master’s degree in Microelectronics, Electronics, Computer Science or relevant disciplines

? Good knowledge on typical IC design flow

? Good knowledge on Verilog, C/C++ and scripting languages (Perl, Python, etc.)

? Experience on using simulator (VCS/Questasim/IUS) and debug tool (Verdi)