? Understand RTL design specification and compose verification plan

? Develop verification testbench and stimulus

? Analyze and conclude root cause for issues and failures

? Understand the latest in-house and industrial standard verification methodologies and develop new methodologies

? Bachelor or master’s degree in Microelectronics, Electronics, Computer Science or relevant disciplines

? Good knowledge on typical IC design flow

? Good knowledge on Verilog, C/C++ and scripting languages (Perl, Python, etc.)