We're looking for SoC timing & FCT integration DE to join our team of Full Chip Timing Backend Integration which is a part of the C2DG Design group.

What will you do in this role:

Static timing analysis work with POs & BU data integration to FCT models and debug.

Be responsible for arch timing paths to enable SoC FCT convergence.

You will work closely with worldwide CPU design teams on FC timing flows.

If you want to leave your marking on future FC timing - join us!

Qualifications

3-5 years of experience in Hardware Backend design and STA

B.SC in Electrical Engineering or Computers Engineering or Computer and Software Engineering

The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.