At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Sr. Principal Engineer will be a senior member of the Hardware Verification Research and Development team working in the field of EDA algorithmic software development for verification hardware. You will be working with your energetic team members on providing a breakthrough solution in the emulation space. Challenges include the design of efficient data structure and algorithms, revisit traditional synthesis algorithms under context of multi-threading and multi-process environment, and a commitment to deliver high quality production software.

Position Requirements:

• You must have a BS/MS/Phd CS,EE,CE and at least 5 years of solid experience as an experienced and highly productive software engineer.
• Strong experience in the EDA software space and have delivered great QoR on an FPGA/ASIC synthesis or FPGA/ASIC verification tool chain or you are an algorithm ninja and wish to make breakthroughs in the exciting hardware verification/emulation space.
• You are confident to own the end to end software chain all the way from RTL mapping to the backend writer, and yet you can work in a high caliber team effectively.
• You are well renowned for your excellent programming skills in C/C++ and you document your work clearly and love talking about it to your team.
• Knowledge of Simulators and HDLs such as Verilog/VHDL and some exposure to multi-threaded/ concurrent programming are pluses.

We’re doing work that matters. Help us solve what others can’t.