• This position presents an excellent opportunity for a highly motivated technical contributor to excel in driving substrate manufacturing process characterization and improvement through Development, Ramp, and High Volume Manufacturing (HVM) phases.
• Work together with supplier and internal partners for planning and execution of process window characterization and validation in the area of warpage interaction between substrate and Assembly/Test, validation of process control plan and FMEA, improvement of process control system and process development methodology.
• Develops solutions to technical problems (warpage) and systemically closes the problems to ensure smooth Ramp and HVM.

Qualifications

1. BS, MS or PhD in science or engineering fields with minimum 8 years of experience in semiconductor (Fab, Substrate, Assembly) development or manufacturing environment is required.
2. Strong skill required for supplier management, quality management, analytical problem solving, and influence in relevant fields of HVM.
3. In-depth knowledge required on substrate manufacturing processes and warpage related Assembly/Test/Substrate interaction, raw material warpage interaction, packaging technologies, and quality and process control system.
4. Fluent communication and articulation skills in business level English, strong presentation skills and ability to effectively communicate and interact with internally and supplier's management highly required.
5. Strong ability to work in cross functional teams are required.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

Japan, Tokyo;Malaysia, Penang;South Korea, Busan;Vietnam, Ho_Chi_Minh_City

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.