Position: Staff Analog Modeling Engineer

Location: Shanghai, China

About IDT, a Renesas Electronics Company

Teamwork, innovation and impact are the root of our corporate culture. IDT/Renesas is seeking individuals who want to maximize their impact on our technology, our customers and company. We recognize that our talented workforce makes us a top performer in our industry. We foster a positive and collaborative environment where ideas are shared and nurtured.

IDT/Renesas is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. IDT/Renesas brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.

Our offer

With one of our top priorities being to attract, retain and develop our world-class workforce, your career or internship at IDT/Renesas is guaranteed to be challenging, stimulating and rewarding - both personally and professionally. We give you the tools, support and resources to put great ideas together into successful products.

Scope and responsibility:

• Communicate with analog designer to understand the circuit function.

• Model analog circuit function with System Verilog NET Type.

• Setup block level mix signal simulation bench

• Do mix-signal simulation and spice simulation to ensure the model and schematic function consistence.

• Support verification engineer for mix signal verification in chip level.

• Extra bandwidth will involve into verification work of test case, reference model and environment development.

  
  

Education，Experience, Preferred Skills & Knowledge:

• MS in EE/CS/ME.

• Minimum of 5 years’ experience.

• Candidate should be familiar with basic analog and digital circuit like OSC,I/O,ADC,DAC.

• Candidate should be familiar with System Verilog and Verilog HDL.

• Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.

• Candidate should be familiar with industry standard ASIC design and verification tools and flow.

• Good knowledge of UVM verification methodology would be added advantage.

• Good knowledge of DDR or HSS basic circuit would be added advantage.

• Good knowledge of Python and shell programming would be an added advantage.

• Independent and self-managing.

  
  

IDT/Renesas is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment regardless of race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.