Responsibilities:

As physical design engineer in COT team in Shanghai, you are expected to provide backend design service to multiple Marvell SOC designs, from synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff to physical verification. You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs, and use your expertise to influence frontend and integration team to ensure successful tapeouts. You will collaborate closely with peer physical design teams from Marvell US and other international sites.

Requirements:

• BS/MS in EE/CS with 5+ years of hands-on experience in SOC physical implementation and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure.
• Proven track records of leading chip level backend implementation activity and taping out complex SOC chips under tight schedule pressure.
• Strong leadership and collaboration skill. Experience of leading large physical design team is a plus.
• Strong knowledge on transistor level custom layout and circuit design/simulation.
• In-depth understanding of current design/process technologies used in major foundries.
• Must be CAD-minded, expert on using automation to improve efficiency and streamline process.
• Detail oriented, self-motivated team player, good verbal and written communication skills.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.