As an integral part of Intel, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.
Role :-
(a) The relevant experience includes CMOS combinatorial logic and sequential, clock cells and special cells layout design.
(b) The candidate should have proven track record of leading Std cells libraries project execution to success.
(c) The candidate should have strong layout design concepts starting from LEF design, floor planning, FIN FET layouts, LVS and DRC clean up, EMIR clean up etc.
(d) The candidate needs to have strong communication skills and problem solving skills.
(e) The responsibilities will include Std Cells library layout design and development on leading edge Intel technologies like 22nm, 7nm, 5nm, 3nm etc.
Qualifications
(a) The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering.
(b) The candidate needs to have relevant experience of 3-10 years in Std Cells libraries porting and layout design and development
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth
Legal Disclaimer:
Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.
Get email alerts for the latest"Standard Cell Libraries Layout Design Engineer jobs in Jr0180535"