At Intel, we drive innovation and break through barriers every single day. We look for remarkable people who understand partnership and have desire to disrupt the status quo. Intel's products support multiple platforms like TikTok, Instagram and Amazon. Our switches process millions of customer transactions, calls and data transmissions without interruption, in seconds.

Creating technology that works that fast, takes talent and passion. We invite you to come join a creative team of engineers dedicated to designing technologies that network the leading cloud-service datacenters. We offer, paid sabbatical, Immediate vesting at 100% of company matched 401k contributions,  Annual and Quarterly Bonuses, Stock Programs,  On-campus health clinics, fitness classes, spas, healthy meals, café options and so much more!  

Structured ASIC team: 

This is a structured ASIC team under Intel’s PSG is targeting 5G, cloud computing and high-end consumer application space. Intel® eASIC™ devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC. 

As a member of Intel's Programmable Solutions group, you will be responsible for developing an IP prototyping platform with a focus on FPGA interface design, verification, and validation, for Intel's high speed SERDES products.

Responsibilities include but not limited to:

• Develop a custom Double Data Rate interface on a Field Programmable Gate Array using Verilog/System Verilog to interface with a Serializer/Deserializer IP test chip: Micro-architecture, Front-end Design, Verification and Board Validation. 

• Productize the interface as an integrable IP for internal and external customers. Support customers with implementation of their logic to be tested with the DDR interface. 

• Create a reference design and lead the execution of a hardware validation plan. 

• Generate collateral (Field Programmable Gate Array reference design, documentation and training).

• Mentor/lead team members to execute on the interface.

• Lead the evolution (revolution) of the interface in subsequent product generations. Provide architectural input in the design/integration of Serializer/Deserializer IP in a programmable SoC environment.

• Excellent written and verbal communication skills.

Qualifications

Minimum Education Requirement:
Bachelor’s degree in Electrical Engineering, Electrical Electronics, Computer Engineering, or related field.

 

Minimum Qualifications:  
5+years of experience in Field Programmable Gate Array RTL (Register Transfer Level) development, verification and FPGA tools, Intel Quartus preferred.
5+years of experience in FPGAs or Application Specific Integrated Circuit , Serializer/Deserializer and networking applications.
5+ years of lab experience handling boards and test equipment such as oscilloscopes.

Preferred Qualifications

• Experience in programming and data analysis with Python or Matlab or Perl or C++ or any Object-Oriented language

• Experience in Serializer/Deserializer IP architecture and implementation

• Experience in digital design

• Experience with MS Office Suite

Inside this Business Group

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.