Value Engineering Engineer
Intel CorporationHsinchuUpdate time: May 11,2022
Job Description

THE ROLE:
Test Value Engineering team is a Cost and Quality driven team responsible for supporting/driving global functional teams to improve test program stability in HVM, yield, and test time. From Early engagement in NPI to Ramp and HVM to achieve operation excellence. This Role is a technical individual contributor role on test program development and represents value engineering team on test excursions and issue escalations to the respective owner to identify resolution or containment action for the issue. Candidate will have plenty of opportunities to work with global functional teams on test solution development and optimizations.


THE PERSON:
Position involves test program development, data analysis, debug, preferably with experience in area of Product Test Program development, hardware DIB design requirements, and knowledge of IP level tests bring up. A proactive, outstanding teammate who focuses on teamwork with good communication skill.


KEY RESPONSIBILITIES:

  • Responsible for ensuring the test stability and manufacturability of wafer sort and final test after production ramp.
  • Make significant contributions to wafer sort and final test yield improvement, site-to-site yield gap elimination and yield gap reduction.
  • Drives test KPI improvement (test yield, test time, coverage issues) and able to integrate, develop and debug ATE test program.
  • Works with internal cross-function teams, BUs, and external manufacturing partners (OSATs) to ensure optimal match of test requirements with production equipment capability with specific emphasis on yield analysis and improvement capability.
  • Responsible for cost-saving and freeing up test capacity through test time reduction and improve test hardware optimizations (e.g. increased parallelism).
  • Works with BUs on test time reduction through identifying no-fail patterns or tests with high volume test data analysis.
  • Drives test platform conversion to support test capacity flexibility.
  • Enabling advance wafer yield analysis through sort program improvements.


Qualifications

QUALIFICATION/PREFERRED EXPERIENCE:

  • Bachelor/Master's degree in Electronic Engineering or Computer Engineering.
  • 5+ years of experience in semiconductor product test development.
  • 5+ years ATE experience with Advantest V93K, T2K or Teradyne J750/EX ATE platform.
  • 5+ years of experience with developing tests, patterns/vectors, timing, and diagnostics on Automated Test Equipment. IP knowledge on either SCAN, MBIST, HSIO, DDR, Thermal and RF test development experience.
  • Strong programming skill on C/C++, VB, Java, Python.
  • Familiar with both wafer probers, probe technology, handler, automated thermal control
  • PCB design along with electric and components is a PLUS.
  • Strong pareto analysis experience to drive a debug process and problem-solving skills.
  • Good communication skills and able to interface/communicate effectively with all levels, BU and OSATs.

Inside this Business Group

Intel's Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.



Other Locations

Singapore, Multiple Cities



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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