Design Verification Engineer(2019)
MediaTek新竹市Update time: September 14,2019
Job Description
1. MCU/AI design verification
2. Familiar with verification methodology including UVM, Formal and portable stimulus
3. Familiar ESL modeling and SoC architecture analysis is plus
4. Familiar with Emulator and FPGA is plus
Requirement
1. MCU/AI design verification
2. Familiar with verification methodology including UVM, Formal and portable stimulus
3. Familiar ESL modeling and SoC architecture analysis is plus
4. Familiar with Emulator and FPGA is plus
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