76426_IP verification Engineer
AMDShanghaiUpdate time: July 17,2020
Job Description


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

 

THE PERSON:

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas

 

KEY RESPONSIBILITIES:

  • Understand the ASIC design/verification flow to accomplish targets.
  • Develop infrastructure and environment for IP/SoC level design verification.
  • Closely working with Design/Architecture/Verification team to develop new verification component.

 

PREFERRED EXPERIENCE:

  • Master in Electrical Engineering, Computer Science or related
  • Good understanding on ASIC design verification flow
  • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
  • Knowledge on Perl, OVL, SVA, SV, UVM, OVM, script programming etc.

 

ACADEMIC CREDENTIALS:

  • Master in EE related major

 

LOCATION:

  • Shanghai

#LI-BY1



Requisition Number: 76426 
Country: China State: Shanghai City: Shanghai 
Job Function: Design

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