Responsibilities

• The development of new environments, execution of verification plans while interfacing with design teams, and debugging problems;
• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification
• scenarios;
• Driving improvements in methodology to achieve greater quality of verification;
• Responsible for the full life cycle of verification, from verification planning to test execution to collecting and closing coverage;
• Identify and write all types of coverage measures for stimulus and corner-cases;

Requirement

• Bachelor in Electronic Engineering;
• 2 years of relevant experience, less experience or fresh graduates are also welcomed;
• Experience with verification methodology such as UVM/OVM/VMM;
• Experience with SystemVerilog, Verilog and SVA;
• Knowledge of and experience with industry-standard simulators, revision control systems and regression systems;
• Experience with C/C++, Linux Shell Scripting, Perl and TCL ;
• Strong communicator and team player;

We offer attractive compensation package (including 5-day work, medical and dental insurance) to the right candidates according to your academic background and working experience. Interested parties please send your full CV with RECENT and EXPECTED salary to HR Department by clicking 立即申請 or visit our website .

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